In the past as well as today, the majority of semiconductor chips are encapsulated in plastic packages before they are attached to substrates or motherboards. A smaller yet rapidly growing number of semiconductor chips is assembled directly onto substrates in a technology called flip-chip. The principal features of this direct-chip-attach method are depicted in FIG. 1. The integrated circuit (IC) of a semiconductor chip 10 requires bonding pads 11 with a multi-layer metallization and solder material 12, usually referred to as bumps or balls, even if they are not strictly spherical (they may actually more resemble half-domes, semi-spheres, or truncated cones). For better tolerance of thermomechanical stress, these solder balls contain often enough solder material to resemble columns or hour-glasses with concave surface contours. In the standard process, the chip is flipped upside down, brought in contact with contact pads 13 on the first surface of substrate 14, and subjected to the melting temperature of the solder alloy so that the solder reflows. After cooling, the chip 10 is attached to the substrate 14. The gap between the chip and the substrate and the space between the solder joints has to be filled with plastic underfill material 15 in order to mitigate thermomechanical stress and reduce reliability risks on the solder joints. Conductive routing strips are integral with substrate 14. They connect the contact pads 13 to terminal pads 16 on the second surface of substrate 14. Solder balls 17 are disposed on terminal pads 16 for connection to motherboards. The overall assembly of FIG. 1 lends itself to the fabrication of so-called chip-scale with substantially the same outline between chip and substrate. Unfortunately, these packages suffer from the drawback that, in operation and temperature excursions, they are sensitive to thermomechanical stress due to the mismatch between the coefficients of thermal expansion of the semiconductor material and the substrate material.
These reliability risks, as well as the requirements for special pad metallizations, have been described in a series of detailed publications by the International Business Machines Corporation in 1969 (IBM J. Res. Develop., Vol. 13, pp. 226 -296): P. A. Totta et al., SLT Device Metallurgy and its Monolithic Extension, L. F. Miller, Controlled Collapse Reflow Chip Joining, L. S. Goldmann, Geometric Optimization of Controlled Collapse Interconnections, K. C. Norris et al., Reliability ofControled Collapse Interconnections, S. Oktay, Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques, B. S. Berry et al., Studies of the SLT Chip Terminal Metallurgy.
Based on these publications, FIG. 2 illustrated the detail of the metallurgical requirements for the integrated circuit bonding pads 10. A semiconductor chip 10, typically silicon, is protected by a dielectric protective overcoat 20, usually silicon nitride, and a patterned metallization 21 over the aluminum 22 of the circuit bonding pads. Metallization 21 usually consists of a sequence of thin layers, typically a refractory metal 21a, such as chromium, titanium, or tungsten, in contact with the aluminum 22, followed by a solderable metal 21b, such as gold, copper, nickel, or palladium. Finally, solder bump 12 is formed by reflowing the deposited (evaporated or plated) solder alloy. As mentioned, these solder bumps assume various shapes after attaching the chip to the substrate, influenced by the forces of surface tension during the reflow process. The overall process depicted in FIGS. 1 and 2 is expensive, since at least ten process steps are involved: Sputter chromium and copper (or nickel or any of a wide selection of metals described in the literature); spin resist; bake; expose; develop; etch metal; remove resist; seed solder; evaporate or plate solder; reflow solder; flip-chip attach.
During actual operation of the assembly of FIG. 1, significant temperature differences and temperature cycles between semiconductor chip 10 and substrate 14 will appear. Consequently, the reliability of the assembly in FIG. 1 is strongly influenced by the coefficients of thermal expansion of the semiconductor and the substrate. For example, there is more than one order of magnitude difference between the coefficients of thermal expansion of silicon and FR-4. This difference causes thermomechanical stresses which the solder joints 11, 12 and 13 of FIG. 1 have to absorb. Detailed calculations, in the literature references cited above and in others, of the optimum height and volume of the solder joint and the expected onset of thermal fatigue and cracking showed that it is desirable to have
a highly ductile solder; PA1 a high ultimate shear strength of the chip/joint and substrate/joint interfaces; PA1 a large value for the ratio (radius of bump-to-chip contact)/(distance to neutral point of chip).
With the onging trend to increase chip sizes and to reduce area consumption for bonding pads, both driven by cost reduction efforts, the latter goal is obtained ever less and has to substituted by other improvements.
One method aims at absorbing part of the thermomechanical stress on the solder joints by plastic material surrounding the joints and filling the gap between chip and substrate (designated 15 in FIG. 1). See for instance, U.S. patent application Ser. Nos. 60/084,416, 60/084,440, and 60/084,472, filed May 6, 1998 (Thomas et al., Low Stress Method and Apparatus of Underfilling Flip-Chip Electronic Devices). However, this method is expensive, because it represents an additional process step, and it may not be welcome since the customer may have to perform the process after device attachment to the motherboard.
Another method aims at elongating the solder joint after assembly into a column with concave surface contours. However, this method is constrained by solder volume and manufacturability.
Another method aims at intentionally sacrificing solder joints located in extreme locations (for instance, in chip corners) where the stress is highest, in order to save the majority of joints from failure. However, this method consumes valuable semiconductor real estate and it thus expensive; it is generally more a defense against the problem than an avoidance of the problem.
Another method aims at designing electrical redundancy of chip input/output terminals; see for instance U.S. patent application Ser. No. 60/080,122, filed Mar. 31, 1998 (Ibnabdeljalil et al., Electrical Redundancy for Improved Mechanical Reliability in Ball Grid Array Packages). However, this method consumes valuable input/output terminals and semiconductor real estate, and is thus expensive; it is generally more a defense against the problem than an avoidance of the problem.
Consequently, an urgent need has therefore arisen for a coherent, low-cost method of fabricating flip-chip assembly of semiconductor devices offering a fundamental solution for thermomechanical stress reliability. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should allow the usage of various formulations of substrate material, and should achieve improvements toward the goal of small outline and low profile packages. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.